The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to complementary metal oxide semiconductor (CMOS) vertical field effect transistors (VFETs) having source and drain contacts formed using trench solid or liquid phase epitaxy (SPE/LPE).
Field effect transistors (FETs) have been known for a number of years and are now the transistor of choice for use in complex integrated digital circuits. In general, field effect transistors can be fabricated somewhat more simply and with larger process windows than bipolar transistors and, additionally, allow simplified circuit and device design. Constraints on transistor footprint size and current-carrying capacity are continually increasing to satisfy demands for higher digital switching performance, increased functionality and economy of manufacture.
CMOS technology is currently the dominant technology for the manufacture of inverters and other logic gates used in digital integrated circuits, including microprocessors, microcontrollers, or static random access memory (SRAM). The word “complementary” refers to the fact that a typical CMOS circuit use complementary pairs of hole-type (positive) and electron-type (negative) FETs, i.e., p-FETs and n-FETs, respectively. In the “on” state, the n-FET uses electrons as the current carriers in its channel in combination with n-doped source and drain junctions. In the “on” state, the p-FET uses holes as the current carriers in its channel in combination with p-doped source and drain junctions. In the “off” state, the n-FET and p-FET channels are void or fully depleted of electrons and holes, respectively. The transistor channels are typically made from a lightly doped semiconductor of opposite type: p-type for n-FET and n-type for p-FET to ensure the absence of conduction in the “off” state. Furthermore, in combination with the channel doping, respective n-FET and p-FET gates are made from different materials to properly set n-FET and p-FET threshold voltages, the respective gate voltages at which these transistors transition from the “off” state to the “on” state.
Traditional CMOS fabrication techniques include process flows for constructing planar transistors. With planar transistors, transistor density can be increased by decreasing the pitch between transistor gate elements. However, with planar transistors, the ability to decrease gate pitch is limited by the required gate length and spacer thickness. In recent years, there has been significant research and development with regard to nonplanar transistor architectures. Some non-planar transistor architectures, such as VFETs, employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. In VFETs the source to drain current flows in a direction that is perpendicular to a major surface of the substrate. For example, in a known VFET configuration a major substrate surface is horizontal and a vertical fin or nanowire extends upward from the substrate surface. The fin or nanowire forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while the gate is disposed on one or more of the fin or nanowire sidewalls.
Decoupling the gate length from the gate pitch greatly improves the scaling of transistor density. With VFETs device scaling is determined by how closely conductive via contacts can be placed to source/drain and gate regions of the transistor. Unlike planar transistors, however, aggressive scaling of the VFET architecture has placed practical constraints on the maximum available width for the bottom source/drain (S/D) contact. Decreasing the width of the bottom S/D contact to satisfy progressively smaller VFET scaling factors has resulted in a gradual increase of the bottom S/D contact resistance, and consequently, to reductions in device performance. In addition, reducing contact via dimensions has resulted in an increase of the top S/D contact resistance, further degrading device performance. Accordingly, high-performance scaled-down VFET architectures require forming highly-doped and highly-activated semiconducting S/D regions that enable a good conduction into the channel and a low contact resistance between metallic via and semiconducting S/D materials. Because forming S/D regions and/or contacts occurs after forming transistor gates, there is also a practical constraint on the thermal budget for S/D and contact processes imposed by the stability of gate materials, often expressed as a maximum allowable transistor threshold voltage shift of several tens of millivolts.